diff options
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/csrs.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 6424e03..794bdb5 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1852,10 +1852,6 @@ sscsrind_reg_csr_t::sscsrind_reg_csr_t(processor_t* const proc, const reg_t addr } void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const { - if (state->v && state->prv == PRV_U) { - throw trap_virtual_instruction(insn.bits()); - } - if (proc->extension_enabled(EXT_SMSTATEEN)) { if ((state->prv < PRV_M) && !(state->mstateen[0]->read() & MSTATEEN0_CSRIND)) throw trap_illegal_instruction(insn.bits()); @@ -1864,6 +1860,10 @@ void sscsrind_reg_csr_t::verify_permissions(insn_t insn, bool write) const { throw trap_virtual_instruction(insn.bits()); } + if (state->v && state->prv == PRV_U) { + throw trap_virtual_instruction(insn.bits()); + } + // Don't call base verify_permission for VS registers remapped to S-mode if (insn.csr() == address) csr_t::verify_permissions(insn, write); |