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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-01 14:44:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-01 14:44:42 -0700 |
| commit | 75f2a05df9cdff6f3faba748065b3184b9f01b01 (patch) | |
| tree | 634ef6316fc2aad26ff9100f38c5367ebe30f31b /spike_main | |
| parent | 4859971a8879728378b0867e899b082e67737728 (diff) | |
| download | spike-75f2a05df9cdff6f3faba748065b3184b9f01b01.zip spike-75f2a05df9cdff6f3faba748065b3184b9f01b01.tar.gz spike-75f2a05df9cdff6f3faba748065b3184b9f01b01.tar.bz2 | |
Set default entry point from ELF
Diffstat (limited to 'spike_main')
| -rw-r--r-- | spike_main/spike.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 5abdf24..d69d4bc 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -27,7 +27,7 @@ static void help() fprintf(stderr, " -h Print this help message\n"); fprintf(stderr, " -H Start halted, allowing a debugger to connect\n"); fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA); - fprintf(stderr, " --pc=<address> Set the initial program counter [default 0x80000000]\n"); + fprintf(stderr, " --pc=<address> Override ELF entry point\n"); fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n"); fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n"); fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n"); @@ -75,7 +75,7 @@ int main(int argc, char** argv) bool log = false; bool dump_dts = false; size_t nprocs = 1; - reg_t start_pc = DRAM_BASE; + reg_t start_pc = reg_t(-1); std::vector<std::pair<reg_t, mem_t*>> mems; std::unique_ptr<icache_sim_t> ic; std::unique_ptr<dcache_sim_t> dc; |