rvv: remove the option of vector misaligned access

9 files changed, 30 insertions, 43 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index 6a09085..41df79a 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -361,8 +361,6 @@ inline long double to_f(float128_t f){long double r; memcpy(&r, &f, sizeof(r));
 #define DEBUG_RVV_FMA_VF 0
 #endif
 
-extern bool g_vector_mistrap;
-
 //
 // vector: masking skip helper
 //
@@ -1504,7 +1502,7 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
         val = P.VU.elt<uint64_t>(vs3 + fn * vlmul, vreg_inx); \
         break; \
       } \
-      MMU.store_##st_width(baseAddr + (stride) + (offset) * elt_byte, val, g_vector_mistrap); \
+      MMU.store_##st_width(baseAddr + (stride) + (offset) * elt_byte, val); \
     } \
   } \
   P.VU.vstart = 0; 
@@ -1575,7 +1573,7 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
     for (reg_t fn = 0; fn < nf; ++fn) { \
       itype##64_t val; \
       try { \
-        val = MMU.load_##itype##tsew(baseAddr + (i * nf + fn) * (tsew / 8), g_vector_mistrap); \
+        val = MMU.load_##itype##tsew(baseAddr + (i * nf + fn) * (tsew / 8)); \
       } catch (trap_t& t) { \
         if (i == 0) \
           throw; /* Only take exception on zeroth element */ \
diff --git a/riscv/insns/vl1r_v.h b/riscv/insns/vl1r_v.h
index d2a184f..09f4040 100644
--- a/riscv/insns/vl1r_v.h
+++ b/riscv/insns/vl1r_v.h
@@ -3,7 +3,7 @@ require_vector;
 const reg_t baseAddr = RS1;
 const reg_t vd = insn.rd();
 for (reg_t i = 0; i < P.VU.vlenb; ++i) {
-  auto val = MMU.load_uint8(baseAddr + i, g_vector_mistrap);
+  auto val = MMU.load_uint8(baseAddr + i);
   P.VU.elt<uint8_t>(vd, i, true) = val;
 }
 P.VU.vstart = 0;
diff --git a/riscv/insns/vs1r_v.h b/riscv/insns/vs1r_v.h
index 8d26574..0dfc537 100644
--- a/riscv/insns/vs1r_v.h
+++ b/riscv/insns/vs1r_v.h
@@ -4,6 +4,6 @@ const reg_t baseAddr = RS1;
 const reg_t vs3 = insn.rd();
 for (reg_t i = 0; i < P.VU.vlenb; ++i) {
   auto val = P.VU.elt<uint8_t>(vs3, i);
-  MMU.store_uint8(baseAddr + i, val, g_vector_mistrap);
+  MMU.store_uint8(baseAddr + i, val);
 }
-P.VU.vstart = 0; 
+P.VU.vstart = 0;
diff --git a/riscv/insns/vsuxb_v.h b/riscv/insns/vsuxb_v.h
index 86aa2b5..691fb1b 100644
--- a/riscv/insns/vsuxb_v.h
+++ b/riscv/insns/vsuxb_v.h
@@ -15,19 +15,19 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   switch (P.VU.vsew) {
   case e8:
     MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint8_t>(vs3, vreg_inx), g_vector_mistrap);
+                    P.VU.elt<uint8_t>(vs3, vreg_inx));
     break;
   case e16:
     MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
+                    P.VU.elt<uint16_t>(vs3, vreg_inx));
     break;
   case e32:
     MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+                    P.VU.elt<uint32_t>(vs3, vreg_inx));
     break;
   case e64:
     MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+                    P.VU.elt<uint64_t>(vs3, vreg_inx));
     break;
   }
 }
diff --git a/riscv/insns/vsuxe_v.h b/riscv/insns/vsuxe_v.h
index 1e4d150..438ca6a 100644
--- a/riscv/insns/vsuxe_v.h
+++ b/riscv/insns/vsuxe_v.h
@@ -16,19 +16,19 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   switch (sew) {
   case e8:
     MMU.store_uint8(baseAddr + index[i],
-                    P.VU.elt<uint8_t>(vs3, vreg_inx), g_vector_mistrap);
+                    P.VU.elt<uint8_t>(vs3, vreg_inx));
     break;
   case e16:
     MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint16_t>(vs3, vreg_inx));
     break;
   case e32:
     MMU.store_uint32(baseAddr + index[i],
-                     P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint32_t>(vs3, vreg_inx));
     break;
   case e64:
     MMU.store_uint64(baseAddr + index[i],
-                     P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint64_t>(vs3, vreg_inx));
     break;
   }
 }
diff --git a/riscv/insns/vsuxh_v.h b/riscv/insns/vsuxh_v.h
index bc39a50..28d2d91 100644
--- a/riscv/insns/vsuxh_v.h
+++ b/riscv/insns/vsuxh_v.h
@@ -15,15 +15,15 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   switch (P.VU.vsew) {
   case e16:
     MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint16_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint16_t>(vs3, vreg_inx));
     break;
   case e32:
     MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint32_t>(vs3, vreg_inx));
     break;
   case e64:
     MMU.store_uint16(baseAddr + index[i],
-                     P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint64_t>(vs3, vreg_inx));
     break;
   }
 }
diff --git a/riscv/insns/vsuxw_v.h b/riscv/insns/vsuxw_v.h
index 48d64ff..0ee1f4b 100644
--- a/riscv/insns/vsuxw_v.h
+++ b/riscv/insns/vsuxw_v.h
@@ -15,11 +15,11 @@ for (reg_t i = 0; i < vlmax && vl != 0; ++i) {
   switch (P.VU.vsew) {
   case e32:
     MMU.store_uint32(baseAddr + index[i],
-                     P.VU.elt<uint32_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint32_t>(vs3, vreg_inx));
     break;
   case e64:
     MMU.store_uint32(baseAddr + index[i],
-                     P.VU.elt<uint64_t>(vs3, vreg_inx), g_vector_mistrap);
+                     P.VU.elt<uint64_t>(vs3, vreg_inx));
     break;
   }
 }
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 485371e..c200084 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -58,32 +58,23 @@ public:
   mmu_t(simif_t* sim, processor_t* proc);
   ~mmu_t();
 
-  inline reg_t misaligned_load(reg_t addr, size_t size, bool mistrap)
+  inline reg_t misaligned_load(reg_t addr, size_t size)
   {
 #ifdef RISCV_ENABLE_MISALIGNED
-    if (mistrap) {
-      throw trap_load_address_misaligned(addr);
-    } else {
-      reg_t res = 0;
-      for (size_t i = 0; i < size; i++)
-        res += (reg_t)load_uint8(addr + i) << (i * 8);
-      return res;
-    }
+    reg_t res = 0;
+    for (size_t i = 0; i < size; i++)
+      res += (reg_t)load_uint8(addr + i) << (i * 8);
+    return res;
 #else
     throw trap_load_address_misaligned(addr);
 #endif
   }
 
-  inline void misaligned_store(reg_t addr, reg_t data, size_t size,
-                               bool mistrap)
+  inline void misaligned_store(reg_t addr, reg_t data, size_t size)
   {
 #ifdef RISCV_ENABLE_MISALIGNED
-    if (mistrap) {
-      throw trap_store_address_misaligned(addr);
-    } else {
-        for (size_t i = 0; i < size; i++)
-          store_uint8(addr + i, data >> (i * 8));
-    }
+    for (size_t i = 0; i < size; i++)
+      store_uint8(addr + i, data >> (i * 8));
 #else
     throw trap_store_address_misaligned(addr);
 #endif
@@ -98,9 +89,9 @@ public:
 
   // template for functions that load an aligned value from memory
   #define load_func(type) \
-    inline type##_t load_##type(reg_t addr, bool mistrap = false) { \
+    inline type##_t load_##type(reg_t addr) { \
       if (unlikely(addr & (sizeof(type##_t)-1))) \
-        return misaligned_load(addr, sizeof(type##_t), mistrap); \
+        return misaligned_load(addr, sizeof(type##_t)); \
       reg_t vpn = addr >> PGSHIFT; \
       size_t size = sizeof(type##_t); \
       if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) { \
@@ -144,9 +135,9 @@ public:
 
   // template for functions that store an aligned value to memory
   #define store_func(type) \
-    void store_##type(reg_t addr, type##_t val, bool mistrap = false) { \
+    void store_##type(reg_t addr, type##_t val) { \
       if (unlikely(addr & (sizeof(type##_t)-1))) \
-        return misaligned_store(addr, val, sizeof(type##_t), mistrap); \
+        return misaligned_store(addr, val, sizeof(type##_t)); \
       reg_t vpn = addr >> PGSHIFT; \
       size_t size = sizeof(type##_t); \
       if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) { \
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 2649707..dd7b35d 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -16,8 +16,6 @@
 #include <sys/wait.h>
 #include <sys/types.h>
 
-bool g_vector_mistrap = false;
-
 volatile bool ctrlc_pressed = false;
 static void handle_signal(int sig)
 {