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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-26 23:26:45 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-26 23:26:45 -0700 |
| commit | 9a5c4ade252d3ad9b78f124d2fb2d8ae60a1de51 (patch) | |
| tree | 19a10427991215cce64ee6568a601505a274db32 /riscv | |
| parent | c29c9f562861495ad57b32adf1d11751c16903aa (diff) | |
| download | spike-9a5c4ade252d3ad9b78f124d2fb2d8ae60a1de51.zip spike-9a5c4ade252d3ad9b78f124d2fb2d8ae60a1de51.tar.gz spike-9a5c4ade252d3ad9b78f124d2fb2d8ae60a1de51.tar.bz2 | |
rvv: fix vssraa.vi e64 corner case
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/insns/vssra_vi.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/vssra_vi.h b/riscv/insns/vssra_vi.h index c854ca6..ff2e1c5 100644 --- a/riscv/insns/vssra_vi.h +++ b/riscv/insns/vssra_vi.h @@ -3,7 +3,7 @@ VRM xrm = P.VU.get_vround_mode(); VI_VI_LOOP ({ int sh = simm5 & (sew - 1) & 0x1f; - int64_t val = vs2; + int128_t val = vs2; INT_ROUNDING(val, xrm, sh); vd = val >> sh; |