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author | Tim Newsome <tim@sifive.com> | 2016-07-13 13:26:09 -0700 |
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committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2016-07-13 13:26:09 -0700 |
commit | 75494f3abd1195fb66d6dbe7e6feefc487ac6333 (patch) | |
tree | 80a1bb18b5de6c3da52827a848a1cfc969ab380d /riscv | |
parent | da0bc312aefa12960d65dd0e12aa87ad9a771f2d (diff) | |
download | spike-75494f3abd1195fb66d6dbe7e6feefc487ac6333.zip spike-75494f3abd1195fb66d6dbe7e6feefc487ac6333.tar.gz spike-75494f3abd1195fb66d6dbe7e6feefc487ac6333.tar.bz2 |
Fix single step over csrw instructions. (#57)
csrw instructions instantly return if the PC isn't serialized. Take note
of this, and don't enter debug mode until the instruction we just
executed actually completed.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/execute.cc | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index e2e72d6..20567af 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -97,18 +97,22 @@ void processor_t::step(size_t n) { if (unlikely(state.single_step == state.STEP_STEPPING)) { state.single_step = state.STEP_STEPPED; - } else if (unlikely(state.single_step == state.STEP_STEPPED)) { - state.single_step = state.STEP_NONE; - enter_debug_mode(DCSR_CAUSE_STEP); - // enter_debug_mode changed state.pc, so we can't just continue. - break; } insn_fetch_t fetch = mmu->load_insn(pc); if (debug && !state.serialized) disasm(fetch.insn); pc = execute_insn(this, pc, fetch); + bool serialize_before = (pc == PC_SERIALIZE_BEFORE); + advance_pc(); + + if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) { + state.single_step = state.STEP_NONE; + enter_debug_mode(DCSR_CAUSE_STEP); + // enter_debug_mode changed state.pc, so we can't just continue. + break; + } } } else while (instret < n) |