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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 21:41:00 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 21:43:22 -0700 |
| commit | 68f33575886a491784b4bf46a3d0b0a249b9809d (patch) | |
| tree | 30cca4b701f07008ec3b50a248eaeef912e8b838 /riscv | |
| parent | 24887186b51e00c8042cdfbec46e1f08a9534e45 (diff) | |
| download | spike-68f33575886a491784b4bf46a3d0b0a249b9809d.zip spike-68f33575886a491784b4bf46a3d0b0a249b9809d.tar.gz spike-68f33575886a491784b4bf46a3d0b0a249b9809d.tar.bz2 | |
rvv: dont't handle slen != vlen
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 17c3f6c..4b99c71 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1524,14 +1524,7 @@ VI_LOOP_END // vector: load/store helper // #define VI_STRIP(inx) \ - reg_t elems_per_strip = P.VU.get_slen()/P.VU.vsew; \ - reg_t elems_per_vreg = P.VU.get_vlen()/P.VU.vsew; \ - reg_t elems_per_lane = P.VU.vlmul * elems_per_strip; \ - reg_t strip_index = (inx) / elems_per_lane; \ - reg_t index_in_strip = (inx) % elems_per_strip; \ - int32_t lmul_inx = (int32_t)(((inx) % elems_per_lane) / elems_per_strip); \ - reg_t vreg_inx = lmul_inx * elems_per_vreg + strip_index * elems_per_strip + index_in_strip; - + reg_t vreg_inx = inx; #define VI_DUPLICATE_VREG(reg_num, idx_sew) \ reg_t index[P.VU.vlmax]; \ |