rvv: add new vcsr vector csr

new features in spec 0.9

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

3 files changed, 31 insertions, 19 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index abf3b92..feaf2d4 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -34,11 +34,11 @@ const int NCSR = 4096;
 #define X_RA 1
 #define X_SP 2
 
-#define FSR_VXRM_SHIFT 9
-#define FSR_VXRM  (0x3 << FSR_VXRM_SHIFT)
+#define VSR_VXRM_SHIFT 1
+#define VSR_VXRM  (0x3 << VSR_VXRM_SHIFT)
 
-#define FSR_VXSAT_SHIFT 8
-#define FSR_VXSAT  (0x1 << FSR_VXSAT_SHIFT)
+#define VSR_VXSAT_SHIFT 0
+#define VSR_VXSAT  (0x1 << VSR_VXSAT_SHIFT)
 
 #define FP_RD_NE  0
 #define FP_RD_0   1
diff --git a/riscv/encoding.h b/riscv/encoding.h
index 371457f..2729f23 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -1569,6 +1569,7 @@
 #define CSR_VSTART 0x8
 #define CSR_VXSAT 0x9
 #define CSR_VXRM 0xa
+#define CSR_VCSR 0xf
 #define CSR_USCRATCH 0x40
 #define CSR_UEPC 0x41
 #define CSR_UCAUSE 0x42
@@ -2521,6 +2522,7 @@ DECLARE_CSR(utvec, CSR_UTVEC)
 DECLARE_CSR(vstart, CSR_VSTART)
 DECLARE_CSR(vxsat, CSR_VXSAT)
 DECLARE_CSR(vxrm, CSR_VXRM)
+DECLARE_CSR(vcsr, CSR_VCSR)
 DECLARE_CSR(uscratch, CSR_USCRATCH)
 DECLARE_CSR(uepc, CSR_UEPC)
 DECLARE_CSR(ucause, CSR_UCAUSE)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index d3532e0..15c28ae 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -623,10 +623,6 @@ void processor_t::set_csr(int which, reg_t val)
       dirty_fp_state;
       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
-      if (supports_extension('V')) {
-        VU.vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
-        VU.vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
-      }
       break;
     case CSR_MSTATUS: {
       if ((val ^ state.mstatus) &
@@ -829,13 +825,18 @@ void processor_t::set_csr(int which, reg_t val)
       VU.vstart = val;
       break;
     case CSR_VXSAT:
-      dirty_fp_state;
+      dirty_vs_state;
       VU.vxsat = val & 0x1ul;
       break;
     case CSR_VXRM:
-      dirty_fp_state;
+      dirty_vs_state;
       VU.vxrm = val & 0x3ul;
       break;
+    case CSR_VCSR :
+      dirty_vs_state;
+      VU.vxsat = (val & VSR_VXSAT) >> VSR_VXSAT_SHIFT;
+      VU.vxrm = (val & VSR_VXRM) >> VSR_VXRM_SHIFT;
+      break;
   }
 }
 
@@ -889,15 +890,11 @@ reg_t processor_t::get_csr(int which)
         break;
       return state.frm;
     case CSR_FCSR:
-      {require_fp;
+      require_fp;
       if (!supports_extension('F'))
         break;
-      uint32_t shared_flags = 0;
-      if (supports_extension('V'))
-            shared_flags = (VU.vxrm << FSR_VXRM_SHIFT) | (VU.vxsat << FSR_VXSAT_SHIFT);
-      return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT) |
-          shared_flags;
-      }
+      return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
+      
     case CSR_INSTRET:
     case CSR_CYCLE:
       if (ctr_ok)
@@ -1028,26 +1025,39 @@ reg_t processor_t::get_csr(int which)
       return state.dscratch1;
     case CSR_VSTART:
       require_vector_vs;
+      if (!supports_extension('V'))
+        break;
       return VU.vstart;
     case CSR_VXSAT:
-      require_fp;
+      require_vector_vs;
       if (!supports_extension('V'))
         break;
       return VU.vxsat;
     case CSR_VXRM:
-      require_fp;
+      require_vector_vs;
       if (!supports_extension('V'))
         break;
       return VU.vxrm;
     case CSR_VL:
       require_vector_vs;
+      if (!supports_extension('V'))
+        break;
       return VU.vl;
     case CSR_VTYPE:
       require_vector_vs;
+      if (!supports_extension('V'))
+        break;
       return VU.vtype;
     case CSR_VLENB:
       require_vector_vs;
+      if (!supports_extension('V'))
+        break;
       return VU.vlenb;
+    case CSR_VCSR:
+      require_vector_vs;
+      if (!supports_extension('V'))
+        break;
+      return (VU.vxrm << VSR_VXRM_SHIFT) | (VU.vxsat << VSR_VXSAT_SHIFT);
   }
   throw trap_illegal_instruction(0);
 }