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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-06 23:48:08 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-10 00:30:07 -0700 |
| commit | 38802a0ad4984b533a3a558de2b347de5cfaa425 (patch) | |
| tree | 9b357f98ec21e407b51da8ecf21f344aafe2e3e5 /riscv | |
| parent | 109aa23bbf8aba76b27629095688e86643eaf51f (diff) | |
| download | spike-38802a0ad4984b533a3a558de2b347de5cfaa425.zip spike-38802a0ad4984b533a3a558de2b347de5cfaa425.tar.gz spike-38802a0ad4984b533a3a558de2b347de5cfaa425.tar.bz2 | |
rvv: missing vector enabling check for mask operation
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 9b66e25..2c07973 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -555,6 +555,7 @@ static inline bool is_overlapped(const int astart, const int asize, #define VI_LOOP_MASK(op) \ require(P.VU.vsew <= e64); \ + require_vector;\ reg_t vl = P.VU.vl; \ for (reg_t i = P.VU.vstart; i < vl; ++i) { \ int mlen = P.VU.vmlen; \ |