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authorWeiwei Li <liweiwei@iscas.ac.cn>2022-07-17 09:46:09 +0800
committerWeiwei Li <liweiwei@iscas.ac.cn>2022-07-17 09:54:34 +0800
commitf82e54124345f348abaa80ec82d67528a9a8f774 (patch)
treeb43df7994d97aee4e98094bee808182b21256404 /riscv
parent61a2c0ee6306562e084b25e4734d6ae725c475b4 (diff)
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remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIAN
the default target endian is always little endian: - mmu::is_target_big_endian() return false - sim_t::get_target_endianness() return memif_endianness_little when RISCV_ENABLE_DUAL_ENDIAN macro is undefined
Diffstat (limited to 'riscv')
-rw-r--r--riscv/csrs.cc2
-rw-r--r--riscv/sim.cc4
2 files changed, 0 insertions, 6 deletions
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index be23a2e..c27410c 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -493,9 +493,7 @@ reg_t mstatus_csr_t::compute_mstatus_initial_value() const noexcept {
return 0
| (proc->extension_enabled_const('U') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_UXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
| (proc->extension_enabled_const('S') && (proc->get_const_xlen() != 32) ? set_field((reg_t)0, MSTATUS_SXL, xlen_to_uxl(proc->get_const_xlen())) : 0)
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
| (proc->get_mmu()->is_target_big_endian() ? MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE : 0)
-#endif
| 0; // initial value for mstatus
}
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 069e1b5..0000537 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -425,11 +425,7 @@ void sim_t::set_target_endianness(memif_endianness_t endianness)
memif_endianness_t sim_t::get_target_endianness() const
{
-#ifdef RISCV_ENABLE_DUAL_ENDIAN
return debug_mmu->is_target_big_endian()? memif_endianness_big : memif_endianness_little;
-#else
- return memif_endianness_little;
-#endif
}
void sim_t::proc_reset(unsigned id)