Add PLIC emulation

We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.

The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.

Signed-off-by: Anup Patel <anup@brainfault.org>

9 files changed, 492 insertions, 0 deletions

diff --git a/riscv/devices.h b/riscv/devices.h
index 934904a..c9e4f66 100644
--- a/riscv/devices.h
+++ b/riscv/devices.h
@@ -72,6 +72,51 @@ class clint_t : public abstract_device_t {
   std::vector<mtimecmp_t> mtimecmp;
 };
 
+#define PLIC_MAX_DEVICES 1024
+
+struct plic_context {
+	uint32_t num;
+	processor_t *proc;
+	bool mmode;
+
+	uint8_t priority_threshold;
+	uint32_t enable[PLIC_MAX_DEVICES/32];
+	uint32_t pending[PLIC_MAX_DEVICES/32];
+	uint8_t pending_priority[PLIC_MAX_DEVICES];
+	uint32_t claimed[PLIC_MAX_DEVICES/32];
+};
+typedef struct plic_context plic_context_t;
+
+class plic_t : public abstract_device_t, public abstract_interrupt_controller_t {
+ public:
+  plic_t(std::vector<processor_t*>&, bool smode, uint32_t ndev);
+  bool load(reg_t addr, size_t len, uint8_t* bytes);
+  bool store(reg_t addr, size_t len, const uint8_t* bytes);
+  void set_interrupt_level(uint32_t id, int lvl);
+  size_t size() { return PLIC_SIZE; }
+ private:
+  std::vector<processor_t*>& procs;
+  std::vector<plic_context_t> contexts;
+  uint32_t num_ids;
+  uint32_t num_ids_word;
+  uint32_t max_prio;
+  uint8_t priority[PLIC_MAX_DEVICES];
+  uint32_t level[PLIC_MAX_DEVICES/32];
+  uint32_t context_best_pending(plic_context_t *c);
+  void context_update(plic_context_t *context);
+  uint32_t context_claim(plic_context_t *c);
+  bool priority_read(reg_t offset, uint32_t *val);
+  bool priority_write(reg_t offset, uint32_t val);
+  bool context_enable_read(plic_context_t *context,
+                           reg_t offset, uint32_t *val);
+  bool context_enable_write(plic_context_t *context,
+                            reg_t offset, uint32_t val);
+  bool context_read(plic_context_t *context,
+                    reg_t offset, uint32_t *val);
+  bool context_write(plic_context_t *context,
+                     reg_t offset, uint32_t val);
+};
+
 class mmio_plugin_device_t : public abstract_device_t {
  public:
   mmio_plugin_device_t(const std::string& name, const std::string& args);
diff --git a/riscv/dts.cc b/riscv/dts.cc
index 6b47c76..970e0ef 100644
--- a/riscv/dts.cc
+++ b/riscv/dts.cc
@@ -93,6 +93,21 @@ std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz,
          "      reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
                      " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
          "    };\n"
+         "    plic@" << PLIC_BASE << " {\n"
+         "      compatible = \"riscv,plic0\";\n"
+         "      interrupts-extended = <" << std::dec;
+  for (size_t i = 0; i < procs.size(); i++)
+    s << "&CPU" << i << "_intc 11 &CPU" << i << "_intc 9 ";
+  reg_t plicbs = PLIC_BASE;
+  reg_t plicsz = PLIC_SIZE;
+  s << std::hex << ">;\n"
+         "      reg = <0x" << (plicbs >> 32) << " 0x" << (plicbs & (uint32_t)-1) <<
+                     " 0x" << (plicsz >> 32) << " 0x" << (plicsz & (uint32_t)-1) << ">;\n"
+         "      riscv,ndev = <0x" << PLIC_NDEV << ">;\n"
+         "      riscv,max-priority = <0x" << ((1U << PLIC_PRIO_BITS) - 1) << ">;\n"
+         "      #interrupt-cells = <1>;\n"
+         "      interrupt-controller;\n"
+         "    };\n"
          "  };\n"
          "  htif {\n"
          "    compatible = \"ucb,htif0\";\n"
@@ -277,6 +292,28 @@ int fdt_parse_clint(void *fdt, reg_t *clint_addr,
   return 0;
 }
 
+int fdt_parse_plic(void *fdt, reg_t *plic_addr, uint32_t *ndev,
+                   const char *compatible)
+{
+  int nodeoffset, len, rc;
+  const fdt32_t *ndev_p;
+
+  nodeoffset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+  if (nodeoffset < 0)
+    return nodeoffset;
+
+  rc = fdt_get_node_addr_size(fdt, nodeoffset, plic_addr, NULL, "reg");
+  if (rc < 0 || !plic_addr)
+    return -ENODEV;
+
+  ndev_p = (fdt32_t *)fdt_getprop(fdt, nodeoffset, "riscv,ndev", &len);
+  if (!ndev || !ndev_p)
+    return -ENODEV;
+  *ndev = fdt32_to_cpu(*ndev_p);
+
+  return 0;
+}
+
 int fdt_parse_pmp_num(void *fdt, int cpu_offset, reg_t *pmp_num)
 {
   int rc;
diff --git a/riscv/dts.h b/riscv/dts.h
index 6208151..66add51 100644
--- a/riscv/dts.h
+++ b/riscv/dts.h
@@ -21,6 +21,8 @@ int fdt_get_next_subnode(void *fdt, int node);
 
 int fdt_parse_clint(void *fdt, reg_t *clint_addr,
                     const char *compatible);
+int fdt_parse_plic(void *fdt, reg_t *plic_addr, uint32_t *ndev,
+                   const char *compatible);
 int fdt_parse_pmp_num(void *fdt, int cpu_offset, reg_t *pmp_num);
 int fdt_parse_pmp_alignment(void *fdt, int cpu_offset, reg_t *pmp_align);
 int fdt_parse_mmu_type(void *fdt, int cpu_offset, const char **mmu_type);
diff --git a/riscv/platform.h b/riscv/platform.h
index 6618d44..4321e84 100644
--- a/riscv/platform.h
+++ b/riscv/platform.h
@@ -5,6 +5,10 @@
 #define DEFAULT_RSTVEC     0x00001000
 #define CLINT_BASE         0x02000000
 #define CLINT_SIZE         0x000c0000
+#define PLIC_BASE          0x0c000000
+#define PLIC_SIZE          0x01000000
+#define PLIC_NDEV          31
+#define PLIC_PRIO_BITS     4
 #define EXT_IO_BASE        0x40000000
 #define DRAM_BASE          0x80000000
 
diff --git a/riscv/plic.cc b/riscv/plic.cc
new file mode 100644
index 0000000..2d08c8e
--- /dev/null
+++ b/riscv/plic.cc
@@ -0,0 +1,393 @@
+#include <sys/time.h>
+#include "devices.h"
+#include "processor.h"
+
+#define PLIC_MAX_CONTEXTS 15872
+
+/*
+ * The PLIC consists of memory-mapped control registers, with a memory map
+ * as follows:
+ *
+ * base + 0x000000: Reserved (interrupt source 0 does not exist)
+ * base + 0x000004: Interrupt source 1 priority
+ * base + 0x000008: Interrupt source 2 priority
+ * ...
+ * base + 0x000FFC: Interrupt source 1023 priority
+ * base + 0x001000: Pending 0
+ * base + 0x001FFF: Pending
+ * base + 0x002000: Enable bits for sources 0-31 on context 0
+ * base + 0x002004: Enable bits for sources 32-63 on context 0
+ * ...
+ * base + 0x0020FC: Enable bits for sources 992-1023 on context 0
+ * base + 0x002080: Enable bits for sources 0-31 on context 1
+ * ...
+ * base + 0x002100: Enable bits for sources 0-31 on context 2
+ * ...
+ * base + 0x1F1F80: Enable bits for sources 992-1023 on context 15871
+ * base + 0x1F1F84: Reserved
+ * ...		    (higher context IDs would fit here, but wouldn't fit
+ *		     inside the per-context priority vector)
+ * base + 0x1FFFFC: Reserved
+ * base + 0x200000: Priority threshold for context 0
+ * base + 0x200004: Claim/complete for context 0
+ * base + 0x200008: Reserved
+ * ...
+ * base + 0x200FFC: Reserved
+ * base + 0x201000: Priority threshold for context 1
+ * base + 0x201004: Claim/complete for context 1
+ * ...
+ * base + 0xFFE000: Priority threshold for context 15871
+ * base + 0xFFE004: Claim/complete for context 15871
+ * base + 0xFFE008: Reserved
+ * ...
+ * base + 0xFFFFFC: Reserved
+ */
+
+/* Each interrupt source has a priority register associated with it. */
+#define PRIORITY_BASE           0
+#define PRIORITY_PER_ID         4
+
+/*
+ * Each hart context has a vector of interupt enable bits associated with it.
+ * There's one bit for each interrupt source.
+ */
+#define ENABLE_BASE             0x2000
+#define ENABLE_PER_HART         0x80
+
+/*
+ * Each hart context has a set of control registers associated with it.  Right
+ * now there's only two: a source priority threshold over which the hart will
+ * take an interrupt, and a register to claim interrupts.
+ */
+#define CONTEXT_BASE            0x200000
+#define CONTEXT_PER_HART        0x1000
+#define CONTEXT_THRESHOLD       0
+#define CONTEXT_CLAIM           4
+
+#define REG_SIZE                0x1000000
+
+plic_t::plic_t(std::vector<processor_t*>& procs, bool smode, uint32_t ndev)
+  : procs(procs), contexts(procs.size() * (smode ? 2 : 1))
+{
+  size_t i;
+  size_t contexts_per_hart = smode ? 2 : 1;
+  plic_context_t *c;
+
+  num_ids = ndev + 1;
+  num_ids_word = num_ids / 32;
+  if ((num_ids_word * 32) < num_ids)
+    num_ids_word++;
+  max_prio = (1UL << PLIC_PRIO_BITS) - 1;
+  memset(priority, 0, sizeof(priority));
+  memset(level, 0, sizeof(level));
+
+  for (i = 0; i < contexts.size(); i++) {
+    c = &contexts[i];
+    c->num = i;
+    c->proc = procs[i / contexts_per_hart];
+    if (smode) {
+      c->mmode = (i % contexts_per_hart == 0);
+    } else {
+      c->mmode = true;
+    }
+    memset(&c->enable, 0, sizeof(c->enable));
+    memset(&c->pending, 0, sizeof(c->pending));
+    memset(&c->pending_priority, 0, sizeof(c->pending_priority));
+    memset(&c->claimed, 0, sizeof(c->claimed));
+  }
+}
+
+uint32_t plic_t::context_best_pending(plic_context_t *c)
+{
+  uint8_t best_id_prio = 0;
+  uint32_t i, j, id, best_id = 0;
+
+  for (i = 0; i < num_ids_word; i++) {
+    if (!c->pending[i]) {
+      continue;
+    }
+
+    for (j = 0; j < 32; j++) {
+      id = i * 32 + j;
+      if ((num_ids <= id) ||
+          !(c->pending[i] & (1 << j)) ||
+          (c->claimed[i] & (1 << j))) {
+        continue;
+      }
+
+      if (!best_id ||
+          (best_id_prio < c->pending_priority[id])) {
+        best_id = id;
+        best_id_prio = c->pending_priority[id];
+      }
+    }
+  }
+
+  return best_id;
+}
+
+void plic_t::context_update(plic_context_t *c)
+{
+  uint32_t best_id = context_best_pending(c);
+  reg_t mask = c->mmode ? MIP_MEIP : MIP_SEIP;
+
+  c->proc->state.mip->backdoor_write_with_mask(mask, best_id ? mask : 0);
+}
+
+uint32_t plic_t::context_claim(plic_context_t *c)
+{
+  uint32_t best_id = context_best_pending(c);
+  uint32_t best_id_word = best_id / 32;
+  uint32_t best_id_mask = (1 << (best_id % 32));
+
+  if (best_id) {
+    c->claimed[best_id_word] |= best_id_mask;
+  }
+
+  context_update(c);
+  return best_id;
+}
+
+bool plic_t::priority_read(reg_t offset, uint32_t *val)
+{
+  uint32_t id = (offset >> 2);
+
+  if (id == 0 || id >= num_ids) {
+    return false;
+  }
+
+  *val = priority[id];
+  return true;
+}
+
+bool plic_t::priority_write(reg_t offset, uint32_t val)
+{
+  uint32_t id = (offset >> 2);
+
+  if (id == 0 || id >= num_ids) {
+    return false;
+  }
+
+  val &= ((1 << PLIC_PRIO_BITS) - 1);
+  priority[id] = val;
+  return true;
+}
+
+bool plic_t::context_enable_read(plic_context_t *c,
+                                 reg_t offset, uint32_t *val)
+{
+  uint32_t id_word = offset >> 2;
+
+  if (num_ids_word < id_word) {
+    return false;
+  }
+
+  *val = c->enable[id_word];
+  return true;
+}
+
+bool plic_t::context_enable_write(plic_context_t *c,
+                                  reg_t offset, uint32_t val)
+{
+  uint8_t id_prio;
+  uint32_t i, id, id_mask;
+  uint32_t id_word = offset >> 2;
+  uint32_t old_val, new_val, xor_val;
+
+  if (num_ids_word < id_word) {
+    return false;
+  }
+
+  old_val = c->enable[id_word];
+  new_val = val;
+
+  if (id_word == 0) {
+    new_val &= ~0x1;
+  }
+
+  c->enable[id_word] = new_val;
+
+  xor_val = old_val ^ new_val;
+  for (i = 0; i < 32; i++) {
+    id = id_word * 32 + i;
+    id_mask = 1 << i;
+    id_prio = priority[id];
+    if (!(xor_val & id_mask)) {
+      continue;
+    }
+    if ((new_val & id_mask) &&
+        (level[id_word] & id_mask)) {
+      c->pending[id_word] |= id_mask;
+      c->pending_priority[id] = id_prio;
+    } else if (!(new_val & id_mask)) {
+      c->pending[id_word] &= ~id_mask;
+      c->pending_priority[id] = 0;
+      c->claimed[id_word] &= ~id_mask;
+    }
+  }
+
+  context_update(c);
+  return true;
+}
+
+bool plic_t::context_read(plic_context_t *c,
+                          reg_t offset, uint32_t *val)
+{
+  bool ret = true;
+
+  switch (offset) {
+  case CONTEXT_THRESHOLD:
+    *val = c->priority_threshold;
+    break;
+  case CONTEXT_CLAIM:
+    *val = context_claim(c);
+    break;
+  default:
+    ret = false;
+    break;
+  };
+
+  return ret;
+}
+
+bool plic_t::context_write(plic_context_t *c,
+                           reg_t offset, uint32_t val)
+{
+  uint32_t id_word, id_mask;
+  bool ret = true, update = false;
+
+  switch (offset) {
+  case CONTEXT_THRESHOLD:
+    val &= ((1 << PLIC_PRIO_BITS) - 1);
+    if (val <= max_prio)
+      c->priority_threshold = val;
+    else
+      update = true;
+    break;
+  case CONTEXT_CLAIM:
+    id_word = val / 32;
+    id_mask = 1 << (val % 32);
+    if ((val < num_ids) &&
+        (c->enable[id_word] & id_mask)) {
+      c->claimed[id_word] &= ~id_mask;
+      update = true;
+    }
+    break;
+  default:
+    ret = false;
+    update = true;
+    break;
+  };
+
+  if (update) {
+    context_update(c);
+  }
+
+  return ret;
+}
+
+void plic_t::set_interrupt_level(uint32_t id, int lvl)
+{
+  uint8_t i, id_prio, id_word;
+  uint32_t id_mask;
+  plic_context_t *c = NULL;
+
+  if (id <= 0 || num_ids <= id) {
+    return;
+  }
+
+  id_prio = priority[id];
+  id_word = id / 32;
+  id_mask = 1 << (id % 32);
+
+  if (lvl) {
+    level[id_word] |= id_mask;
+  } else {
+    level[id_word] &= ~id_mask;
+  }
+
+  /*
+   * Note: PLIC interrupts are level-triggered. As of now,
+   * there is no notion of edge-triggered interrupts. To
+   * handle this we auto-clear edge-triggered interrupts
+   * when PLIC context CLAIM register is read.
+   */
+  for (i = 0; i < contexts.size(); i++) {
+    c = &contexts[i];
+
+    if (c->enable[id_word] & id_mask) {
+      if (lvl) {
+        c->pending[id_word] |= id_mask;
+        c->pending_priority[id] = id_prio;
+      } else {
+        c->pending[id_word] &= ~id_mask;
+        c->pending_priority[id] = 0;
+        c->claimed[id_word] &= ~id_mask;
+      }
+      context_update(c);
+      break;
+    }
+  }
+}
+
+bool plic_t::load(reg_t addr, size_t len, uint8_t* bytes)
+{
+  bool ret = false;
+  uint32_t cntx, val = 0;
+
+  /* Only 32bit loads supported */
+  if (len != 4) {
+    return false;
+  }
+
+  if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) {
+    ret = priority_read(addr, &val);
+  } else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) {
+    cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART;
+    addr -= cntx * ENABLE_PER_HART + ENABLE_BASE;
+    if (cntx < contexts.size()) {
+      ret = context_enable_read(&contexts[cntx], addr, &val);
+    }
+  } else if (CONTEXT_BASE <= addr && addr < REG_SIZE) {
+    cntx = (addr - CONTEXT_BASE) / CONTEXT_PER_HART;
+    addr -= cntx * CONTEXT_PER_HART + CONTEXT_BASE;
+    if (cntx < contexts.size()) {
+      ret = context_read(&contexts[cntx], addr, &val);
+    }
+  }
+
+  if (ret) {
+    memcpy(bytes, (uint8_t *)&val, len);
+  }
+
+  return ret;
+}
+
+bool plic_t::store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+  bool ret = false;
+  uint32_t cntx, val;
+
+  /* Only 32bit stores supported */
+  if (len != 4) {
+    return false;
+  }
+
+  memcpy((uint8_t *)&val, bytes, len);
+
+  if (PRIORITY_BASE <= addr && addr < ENABLE_BASE) {
+    ret = priority_write(addr, val);
+  } else if (ENABLE_BASE <= addr && addr < CONTEXT_BASE) {
+    cntx = (addr - ENABLE_BASE) / ENABLE_PER_HART;
+    addr -= cntx * ENABLE_PER_HART + ENABLE_BASE;
+    if (cntx < contexts.size())
+      ret = context_enable_write(&contexts[cntx], addr, val);
+  } else if (CONTEXT_BASE <= addr && addr < REG_SIZE) {
+    cntx = (addr - CONTEXT_BASE) / CONTEXT_PER_HART;
+    addr -= cntx * CONTEXT_PER_HART + CONTEXT_BASE;
+    if (cntx < contexts.size())
+      ret = context_write(&contexts[cntx], addr, val);
+  }
+
+  return ret;
+}
diff --git a/riscv/processor.h b/riscv/processor.h
index 8797ab1..5c14a36 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -361,6 +361,7 @@ private:
 
   friend class mmu_t;
   friend class clint_t;
+  friend class plic_t;
   friend class extension_t;
 
   void parse_varch_string(const char*);
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 0c6b977..7f1fc9a 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -54,6 +54,7 @@ riscv_srcs = \
 	devices.cc \
 	rom.cc \
 	clint.cc \
+	plic.cc \
 	debug_module.cc \
 	remote_bitbang.cc \
 	jtag_dtm.cc \
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 069e1b5..81a0cbc 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -98,6 +98,14 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
     bus.add_device(clint_base, clint.get());
   }
 
+  // create plic
+  reg_t plic_base;
+  uint32_t plic_ndev;
+  if (fdt_parse_plic(fdt, &plic_base, &plic_ndev, "riscv,plic0") == 0) {
+    plic.reset(new plic_t(procs, true, plic_ndev));
+    bus.add_device(plic_base, plic.get());
+  }
+
   //per core attribute
   int cpu_offset = 0, rc;
   size_t cpu_idx = 0;
diff --git a/riscv/sim.h b/riscv/sim.h
index 97cada1..91b25c2 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -82,6 +82,7 @@ private:
   bool dtb_enabled;
   std::unique_ptr<rom_device_t> boot_rom;
   std::unique_ptr<clint_t> clint;
+  std::unique_ptr<plic_t> plic;
   bus_t bus;
   log_file_t log_file;