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author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2022-12-29 14:04:15 +0300 |
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committer | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-09 19:16:44 +0300 |
commit | 1e6869c17e23a47f9cf62a21eecda32027acebd5 (patch) | |
tree | 524bfcc6926974b5ea73089108cdaa7e76d42de9 /riscv | |
parent | e402a8353d2c4f358198c3bb3de38d40f60c730b (diff) | |
download | spike-1e6869c17e23a47f9cf62a21eecda32027acebd5.zip spike-1e6869c17e23a47f9cf62a21eecda32027acebd5.tar.gz spike-1e6869c17e23a47f9cf62a21eecda32027acebd5.tar.bz2 |
get_inclusive_end implementation for mem_cfg_t
The method can simplify proper processing of sitiations when
(base + size) overflows 64-bit interger.
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/cfg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/cfg.h b/riscv/cfg.h index dba0b37..1fb358f 100644 --- a/riscv/cfg.h +++ b/riscv/cfg.h @@ -49,6 +49,10 @@ public: return size; } + reg_t get_inclusive_end() const { + return base + size - 1; + } + private: reg_t base; reg_t size; |