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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-22 21:38:39 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-29 21:35:22 -0700 |
| commit | fabc3c44845b59931a5a5ed629e0e9178661cc88 (patch) | |
| tree | bc92fd3314f2552b6a9a9170cba981684d11854c /riscv | |
| parent | 3784c3f681c49602470bb3e8c66fa141d030a517 (diff) | |
| download | spike-fabc3c44845b59931a5a5ed629e0e9178661cc88.zip spike-fabc3c44845b59931a5a5ed629e0e9178661cc88.tar.gz spike-fabc3c44845b59931a5a5ed629e0e9178661cc88.tar.bz2 | |
rvv: initialize vector register as zero
some dump and comparison tool may depennd the initial state of
vector register.
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 798c1c2..4bf86da 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -386,7 +386,8 @@ void processor_t::vectorUnit_t::reset(){ VLEN = get_vlen(); ELEN = get_elen(); SLEN = get_slen(); // registers are simply concatenated - reg_file = malloc(NVPR * (VLEN/8)); + reg_file = malloc(NVPR * vlenb); + memset(reg_file, 0, NVPR * vlenb); vtype = 0; set_vl(0, 0, 0, -1); // default to illegal configuration |