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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-23 01:04:42 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-29 21:38:43 -0700 |
| commit | cdda51cb0af8f846ab10bb8d9c1af3aab6a21b46 (patch) | |
| tree | da2e5d59f50f1774712411c8d82d4b7cb3e55c88 /riscv | |
| parent | effb92a5ecca543e27bb0ae3d7c42eee34d4ddf4 (diff) | |
| download | spike-cdda51cb0af8f846ab10bb8d9c1af3aab6a21b46.zip spike-cdda51cb0af8f846ab10bb8d9c1af3aab6a21b46.tar.gz spike-cdda51cb0af8f846ab10bb8d9c1af3aab6a21b46.tar.bz2 | |
rvv: add vrgatherei16.vv
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/encoding.h | 3 | ||||
| -rw-r--r-- | riscv/insns/vrgatherei16_vv.h | 33 | ||||
| -rw-r--r-- | riscv/riscv.mk.in | 1 |
3 files changed, 37 insertions, 0 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 2e18963..f8628c7 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1442,6 +1442,8 @@ #define MASK_VXOR_VV 0xfc00707f #define MATCH_VRGATHER_VV 0x30000057 #define MASK_VRGATHER_VV 0xfc00707f +#define MATCH_VRGATHEREI16_VV 0x38000057 +#define MASK_VRGATHEREI16_VV 0xfc00707f #define MATCH_VADC_VVM 0x40000057 #define MASK_VADC_VVM 0xfe00707f #define MATCH_VMADC_VVM 0x44000057 @@ -2722,6 +2724,7 @@ DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) +DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) diff --git a/riscv/insns/vrgatherei16_vv.h b/riscv/insns/vrgatherei16_vv.h new file mode 100644 index 0000000..780b0ee --- /dev/null +++ b/riscv/insns/vrgatherei16_vv.h @@ -0,0 +1,33 @@ +// vrgatherei16.vv vd, vs2, vs1, vm # vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; +float vemul = (16.0 / P.VU.vsew * P.VU.vflmul); +require(vemul >= 0.125 && vemul <= 8); +require_align(insn.rd(), P.VU.vflmul); +require_align(insn.rs2(), P.VU.vflmul); +require_align(insn.rs1(), vemul); +require(insn.rd() != insn.rs2() && insn.rd() != insn.rs1()); +require_vm; + +VI_LOOP_BASE + switch (sew) { + case e8: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint8_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint8_t>(rs2_num, vs1); + break; + } + case e16: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint16_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint16_t>(rs2_num, vs1); + break; + } + case e32: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint32_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint32_t>(rs2_num, vs1); + break; + } + default: { + auto vs1 = P.VU.elt<uint16_t>(rs1_num, i); + P.VU.elt<uint64_t>(rd_num, i, true) = vs1 >= P.VU.vlmax ? 0 : P.VU.elt<uint64_t>(rs2_num, vs1); + break; + } + } +VI_LOOP_END; diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index ad1c886..6a86158 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -472,6 +472,7 @@ riscv_insn_ext_v_alu_int = \ vrgather_vi \ vrgather_vv \ vrgather_vx \ + vrgatherei16_vv \ vrsub_vi \ vrsub_vx \ vsadd_vi \ |