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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-21 11:07:54 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-29 21:38:43 -0700 |
| commit | 5a107c6ba774bda1de1de78c1b3bc0b847f8092b (patch) | |
| tree | 969e2e915b6967149b64445616503dd4f37588b2 /riscv | |
| parent | 9fadb08893847f137b612e9e83b3849bf67861a5 (diff) | |
| download | spike-5a107c6ba774bda1de1de78c1b3bc0b847f8092b.zip spike-5a107c6ba774bda1de1de78c1b3bc0b847f8092b.tar.gz spike-5a107c6ba774bda1de1de78c1b3bc0b847f8092b.tar.bz2 | |
f16: fix Nan-Box macro
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index d564d08..9f8f786 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -303,7 +303,7 @@ class wait_for_interrupt_t {}; /* Convenience wrappers to simplify softfloat code sequences */ #define isBoxedF16(r) (isBoxedF32(r) && ((uint64_t)((r.v[0] >> 16) + 1) == ((uint64_t)1 << 48))) -#define unboxF16(r) (isBoxedF16(r) ? (uint32_t)r.v[0] : defaultNaNF16UI) +#define unboxF16(r) (isBoxedF16(r) ? (uint16_t)r.v[0] : defaultNaNF16UI) #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) #define isBoxedF64(r) ((r.v[1] + 1) == 0) |