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| author | SuHsien Ho <su-hsien.ho@mediatek.com> | 2023-10-04 15:00:49 +0800 |
|---|---|---|
| committer | SuHsien Ho <su-hsien.ho@mediatek.com> | 2024-04-18 13:05:28 +0800 |
| commit | 9ba5bd3171e97560bc28fe555ff7b8404272a3bb (patch) | |
| tree | c0ac867c7df2ce90c83071e93c0ea5f0c6745d70 /riscv/zicfiss.h | |
| parent | 3192ee4d31f481e84281a24d55bb6130e3743668 (diff) | |
| download | spike-9ba5bd3171e97560bc28fe555ff7b8404272a3bb.zip spike-9ba5bd3171e97560bc28fe555ff7b8404272a3bb.tar.gz spike-9ba5bd3171e97560bc28fe555ff7b8404272a3bb.tar.bz2 | |
Add Zicfiss extension from CFI extension, v0.4.0
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name.
2. Add new software exception with tval 3 for shadow stack.
3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d.
4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding.
5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page.
6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag.
7. Check special pte(xwr=010) of SS page.
Diffstat (limited to 'riscv/zicfiss.h')
| -rw-r--r-- | riscv/zicfiss.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/riscv/zicfiss.h b/riscv/zicfiss.h new file mode 100644 index 0000000..83c166d --- /dev/null +++ b/riscv/zicfiss.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef _RISCV_ZICFISS_H +#define _RISCV_ZICFISS_H + +#define xSSE() \ + ((STATE.prv != PRV_M) && get_field(STATE.menvcfg->read(), MENVCFG_SSE) && \ + p->extension_enabled('S') && \ + ((STATE.v && get_field(STATE.henvcfg->read(), HENVCFG_SSE)) || !STATE.v) && \ + (((STATE.prv == PRV_U) && get_field(STATE.senvcfg->read(), SENVCFG_SSE)) || (STATE.prv != PRV_U))) + +#define PUSH_VALUE_TO_SS(value) ({ \ + reg_t push_value = (value); \ + reg_t push_ssp_addr = STATE.ssp->read() - xlen / 8; \ + if (xlen == 32) \ + MMU.ss_store<uint32_t>(push_ssp_addr, push_value); \ + else \ + MMU.ss_store<uint64_t>(push_ssp_addr, push_value); \ + STATE.ssp->write(push_ssp_addr); \ + }) + +#define POP_VALUE_FROM_SS_AND_CHECK(value) \ + reg_t shadow_return_addr; \ + if (xlen == 32) \ + shadow_return_addr = MMU.ss_load<uint32_t>(STATE.ssp->read()); \ + else \ + shadow_return_addr = MMU.ss_load<uint64_t>(STATE.ssp->read()); \ + software_check(value == shadow_return_addr, SHADOW_STACK_FAULT); \ + STATE.ssp->write(STATE.ssp->read() + xlen / 8); + +#endif |