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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-20 01:48:03 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-05 22:35:10 -0700 |
| commit | 02ef436177b7d9804da0f4b513df64c6bd699555 (patch) | |
| tree | 1d32745ead8d730c803106a55586db3b0a7c60fb /riscv/trap.h | |
| parent | 77e3a7538426c15ae4d6b2bfff99e83493791b77 (diff) | |
| download | spike-02ef436177b7d9804da0f4b513df64c6bd699555.zip spike-02ef436177b7d9804da0f4b513df64c6bd699555.tar.gz spike-02ef436177b7d9804da0f4b513df64c6bd699555.tar.bz2 | |
ebreak should write mtval with 0, not pc
Resolves #426
The relevant passage in the spec does not mention software breakpoints
as one of the cases that cause mtval to be set to a nonzero value:
https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index b5b8a50..ac048eb 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -47,7 +47,7 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) -DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) |