From 02ef436177b7d9804da0f4b513df64c6bd699555 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 20 Mar 2020 01:48:03 -0700 Subject: ebreak should write mtval with 0, not pc Resolves #426 The relevant passage in the spec does not mention software breakpoints as one of the cases that cause mtval to be set to a nonzero value: https://github.com/riscv/riscv-isa-manual/blob/274893e2f0365f904829bbb60fd05cc01d2bfb11/src/machine.tex#L2202 --- riscv/trap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'riscv/trap.h') diff --git a/riscv/trap.h b/riscv/trap.h index b5b8a50..ac048eb 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -47,7 +47,7 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) -DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) -- cgit v1.1