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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 21:01:34 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 21:01:34 -0800 |
| commit | d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be (patch) | |
| tree | d4a1fd090ff86f43eab75b3eb6e1195ab52c59e0 /riscv/trap.h | |
| parent | 692ba09ef40c0cec66304678808db01e23e7b2ec (diff) | |
| download | spike-d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be.zip spike-d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be.tar.gz spike-d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be.tar.bz2 | |
correctly trap when SR_EA is disabled
Diffstat (limited to 'riscv/trap.h')
| -rw-r--r-- | riscv/trap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/trap.h b/riscv/trap.h index 9a1a2f9..bd7e0ee 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -54,5 +54,6 @@ DECLARE_MEM_TRAP(8, load_address_misaligned) DECLARE_MEM_TRAP(9, store_address_misaligned) DECLARE_MEM_TRAP(10, load_access_fault) DECLARE_MEM_TRAP(11, store_access_fault) +DECLARE_TRAP(12, accelerator_disabled) #endif |