From d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Tue, 5 Nov 2013 21:01:34 -0800 Subject: correctly trap when SR_EA is disabled --- riscv/trap.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/trap.h') diff --git a/riscv/trap.h b/riscv/trap.h index 9a1a2f9..bd7e0ee 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -54,5 +54,6 @@ DECLARE_MEM_TRAP(8, load_address_misaligned) DECLARE_MEM_TRAP(9, store_address_misaligned) DECLARE_MEM_TRAP(10, load_access_fault) DECLARE_MEM_TRAP(11, store_access_fault) +DECLARE_TRAP(12, accelerator_disabled) #endif -- cgit v1.1