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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/tracer.h | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | spike-plic_uart_v1.zip spike-plic_uart_v1.tar.gz spike-plic_uart_v1.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/tracer.h')
| -rw-r--r-- | riscv/tracer.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/tracer.h b/riscv/tracer.h index 9f1bc78..d74edae 100644 --- a/riscv/tracer.h +++ b/riscv/tracer.h @@ -5,7 +5,7 @@ #include "processor.h" -static inline void trace_opcode(processor_t* p, insn_bits_t opc, insn_t insn) { +static inline void trace_opcode(processor_t UNUSED *p, insn_bits_t UNUSED opc, insn_t UNUSED insn) { } #endif |