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authorTim Newsome <tim@sifive.com>2019-05-14 11:02:15 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2019-05-29 08:35:12 -0700
commit2af9a7a9e403bee126d78861156019eb94f6b2de (patch)
tree163aafe6ce270eaae8ef81c2d0e021975688b01f /riscv/sim.h
parent1946b11d7400c85f5786d016f4b2ac63e18d7e83 (diff)
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Clean up debug module options. (#299)
* Clean up debug module options. 1. Instead of passing each one a few levels deep, create debug_module_config_t which contains them all. 2. Rename all those command line options so they start with --dm for debug module. 3. Add --dm-no-halt-groups to disable halt group support. * Update changelog. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/sim.h')
-rw-r--r--riscv/sim.h4
1 files changed, 1 insertions, 3 deletions
diff --git a/riscv/sim.h b/riscv/sim.h
index 90e3a5c..d24c1ec 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -24,9 +24,7 @@ public:
sim_t(const char* isa, const char* varch, size_t _nprocs, bool halted,
reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems,
const std::vector<std::string>& args, const std::vector<int> hartids,
- unsigned progsize, unsigned max_bus_master_bits,
- bool require_authentication, suseconds_t abstract_delay_usec,
- bool support_hasel, bool support_abstract_csr_access);
+ const debug_module_config_t &dm_config);
~sim_t();
// run the simulation to completion