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author | Jerry Zhao <jerryz123@berkeley.edu> | 2022-10-25 11:37:44 -0700 |
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committer | Jerry Zhao <jerryz123@berkeley.edu> | 2022-10-25 11:49:33 -0700 |
commit | b265325d19fe9eb9145c65fe110735ff03c1b90c (patch) | |
tree | 5d1826b2eb8f1e0af019c7d1f833880da256f26a /riscv/sim.cc | |
parent | cefccba8cf1008691a1bb5d36bd318e281ffc635 (diff) | |
download | spike-b265325d19fe9eb9145c65fe110735ff03c1b90c.zip spike-b265325d19fe9eb9145c65fe110735ff03c1b90c.tar.gz spike-b265325d19fe9eb9145c65fe110735ff03c1b90c.tar.bz2 |
Remove set_target_endianness | add --big-endian flag
Set target endianess in constructors
Diffstat (limited to 'riscv/sim.cc')
-rw-r--r-- | riscv/sim.cc | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 71ac452..ffb20e4 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -74,11 +74,21 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, debug_module.add_device(&bus); - debug_mmu = new mmu_t(this, NULL); +#ifndef RISCV_ENABLE_DUAL_ENDIAN + if (cfg->endianness != memif_endianness_little) { + fputs("Big-endian support has not been prroperly enabled; " + "please rebuild the riscv-isa-sim project using " + "\"configure --enable-dual-endian\".\n", + stderr); + abort(); + } +#endif + + debug_mmu = new mmu_t(this, cfg->endianness, NULL); for (size_t i = 0; i < cfg->nprocs(); i++) { procs[i] = new processor_t(&isa, cfg->varch(), this, cfg->hartids()[i], halted, - log_file.get(), sout_); + cfg->endianness, log_file.get(), sout_); } make_dtb(); @@ -432,22 +442,6 @@ void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) debug_mmu->store<uint64_t>(taddr, debug_mmu->from_target(data)); } -void sim_t::set_target_endianness(memif_endianness_t endianness) -{ -#ifdef RISCV_ENABLE_DUAL_ENDIAN - assert(endianness == memif_endianness_little || endianness == memif_endianness_big); - - bool enable = endianness == memif_endianness_big; - debug_mmu->set_target_big_endian(enable); - for (size_t i = 0; i < procs.size(); i++) { - procs[i]->get_mmu()->set_target_big_endian(enable); - procs[i]->reset(); - } -#else - assert(endianness == memif_endianness_little); -#endif -} - memif_endianness_t sim_t::get_target_endianness() const { return debug_mmu->is_target_big_endian()? memif_endianness_big : memif_endianness_little; |