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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-17 09:46:09 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-17 09:54:34 +0800 |
| commit | f82e54124345f348abaa80ec82d67528a9a8f774 (patch) | |
| tree | b43df7994d97aee4e98094bee808182b21256404 /riscv/sim.cc | |
| parent | 61a2c0ee6306562e084b25e4734d6ae725c475b4 (diff) | |
| download | spike-f82e54124345f348abaa80ec82d67528a9a8f774.zip spike-f82e54124345f348abaa80ec82d67528a9a8f774.tar.gz spike-f82e54124345f348abaa80ec82d67528a9a8f774.tar.bz2 | |
remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIAN
the default target endian is always little endian:
- mmu::is_target_big_endian() return false
- sim_t::get_target_endianness() return memif_endianness_little
when RISCV_ENABLE_DUAL_ENDIAN macro is undefined
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 069e1b5..0000537 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -425,11 +425,7 @@ void sim_t::set_target_endianness(memif_endianness_t endianness) memif_endianness_t sim_t::get_target_endianness() const { -#ifdef RISCV_ENABLE_DUAL_ENDIAN return debug_mmu->is_target_big_endian()? memif_endianness_big : memif_endianness_little; -#else - return memif_endianness_little; -#endif } void sim_t::proc_reset(unsigned id) |