diff options
| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:24:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:34:25 -0700 |
| commit | d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab (patch) | |
| tree | cbcbf16cef050f44dd8a7d0992878ee142e6f0b0 /riscv/sim.cc | |
| parent | 8d40946475d73ce2627549b1857991d70cb1186b (diff) | |
| download | spike-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.zip spike-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.tar.gz spike-d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab.tar.bz2 | |
Template-ize loads
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 5ce7d21..240133d 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -420,7 +420,7 @@ void sim_t::idle() void sim_t::read_chunk(addr_t taddr, size_t len, void* dst) { assert(len == 8); - auto data = debug_mmu->to_target(debug_mmu->load_uint64(taddr)); + auto data = debug_mmu->to_target(debug_mmu->load<uint64_t>(taddr)); memcpy(dst, &data, sizeof data); } |