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| author | Rupert Swarbrick <rswarbrick@gmail.com> | 2022-02-18 15:45:21 +0000 |
|---|---|---|
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | 2022-03-12 21:51:01 +0000 |
| commit | cb632586bdb1b57ea4e5a5543e21bbb257e47f3b (patch) | |
| tree | 17720758321ebccff687f9d642ac5d14c49df95b /riscv/sim.cc | |
| parent | 59ec157568d2a52feeec568ac042362db1c5ddbc (diff) | |
| download | spike-cb632586bdb1b57ea4e5a5543e21bbb257e47f3b.zip spike-cb632586bdb1b57ea4e5a5543e21bbb257e47f3b.tar.gz spike-cb632586bdb1b57ea4e5a5543e21bbb257e47f3b.tar.bz2 | |
Construct an isa_parser_t and pass it to processor_t constructor
This is a minor change, turning processor_t from a child class of
isa_parser_t into a class that contains an isa_parser_t as a field.
The point is that it is a step toward separating out
"configuration" (and ISA string parsing) from processor state. This
should be helpful for rejigging things so that we construct more from
a supplied device tree.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 8648d5a..064a493 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -28,7 +28,7 @@ static void handle_signal(int sig) signal(sig, &handle_signal); } -sim_t::sim_t(const char* isa, const char* priv, const char* varch, +sim_t::sim_t(const char* isa_string, const char* priv, const char* varch, size_t nprocs, bool halted, bool real_time_clint, reg_t initrd_start, reg_t initrd_end, const char* bootargs, reg_t start_pc, std::vector<std::pair<reg_t, mem_t*>> mems, @@ -43,6 +43,7 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, #endif FILE *cmd_file) // needed for command line option --cmd : htif_t(args), + isa(isa_string, priv), mems(mems), plugin_devices(plugin_devices), procs(std::max(nprocs, size_t(1))), @@ -91,7 +92,7 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, for (size_t i = 0; i < nprocs; i++) { int hart_id = hartids.empty() ? i : hartids[i]; - procs[i] = new processor_t(isa, priv, varch, this, hart_id, halted, + procs[i] = new processor_t(isa, varch, this, hart_id, halted, log_file.get(), sout_); } |