diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-12-13 23:25:32 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-12-14 02:09:43 -0800 |
| commit | bf3a588afd8445a572d1cef07abfd50c3db47f96 (patch) | |
| tree | b98b1f5b57250a5c8e25703030cb0776675c4697 /riscv/sim.cc | |
| parent | 4e3d8df5a8c45c1b3cf3059d0786e947a9f2aba6 (diff) | |
| download | spike-bf3a588afd8445a572d1cef07abfd50c3db47f96.zip spike-bf3a588afd8445a572d1cef07abfd50c3db47f96.tar.gz spike-bf3a588afd8445a572d1cef07abfd50c3db47f96.tar.bz2 | |
dts: mmu: replace 'riscv,bare' by 'riscv,sbare'
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 20895d6..5fff0ed 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -120,14 +120,14 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch, char mmu_type[256] = ""; rc = fdt_parse_mmu_type(fdt, cpu_offset, mmu_type); if (rc == 0) { - procs[cpu_idx]->set_mmu_capability(IMPL_MMU_BARE); + procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SBARE); if (strncmp(mmu_type, "riscv,sv32", strlen("riscv,sv32")) == 0) { procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV32); } else if (strncmp(mmu_type, "riscv,sv39", strlen("riscv,sv39")) == 0) { procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV39); } else if (strncmp(mmu_type, "riscv,sv48", strlen("riscv,sv48")) == 0) { procs[cpu_idx]->set_mmu_capability(IMPL_MMU_SV48); - } else if (strncmp(mmu_type, "riscv,bare", strlen("riscv,bare")) == 0) { + } else if (strncmp(mmu_type, "riscv,sbare", strlen("riscv,sbare")) == 0) { //has been set in the beginning } else { std::cerr << "core (" |