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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:40:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:40:42 -0700 |
| commit | b1f2ae41a1e64f416fb5f5aa092352439ecefa83 (patch) | |
| tree | a5918c9e5ff22fb72c568f9751602ebbd8974d0f /riscv/sim.cc | |
| parent | d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab (diff) | |
| download | spike-b1f2ae41a1e64f416fb5f5aa092352439ecefa83.zip spike-b1f2ae41a1e64f416fb5f5aa092352439ecefa83.tar.gz spike-b1f2ae41a1e64f416fb5f5aa092352439ecefa83.tar.bz2 | |
Template-ize stores
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 240133d..71ac452 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -429,7 +429,7 @@ void sim_t::write_chunk(addr_t taddr, size_t len, const void* src) assert(len == 8); target_endian<uint64_t> data; memcpy(&data, src, sizeof data); - debug_mmu->store_uint64(taddr, debug_mmu->from_target(data)); + debug_mmu->store<uint64_t>(taddr, debug_mmu->from_target(data)); } void sim_t::set_target_endianness(memif_endianness_t endianness) |