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| author | Andrew Waterman <andrew@sifive.com> | 2022-12-29 15:28:50 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-03 16:44:42 -0800 |
| commit | 8d084dbd092a916a2c26d9cb7f30d5651aa3181b (patch) | |
| tree | 770b5acb5576f272f480f8e8ea1c72af7fc72f30 /riscv/sim.cc | |
| parent | 2a95b4e198ed6a3933b55cc86f590dd5d3355b5c (diff) | |
| download | spike-8d084dbd092a916a2c26d9cb7f30d5651aa3181b.zip spike-8d084dbd092a916a2c26d9cb7f30d5651aa3181b.tar.gz spike-8d084dbd092a916a2c26d9cb7f30d5651aa3181b.tar.bz2 | |
Pass cfg object to processor_t constructor
This reduces boilerplate as we add additional options.
Diffstat (limited to 'riscv/sim.cc')
| -rw-r--r-- | riscv/sim.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index 84ff98c..1de3906 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -98,8 +98,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted, debug_mmu = new mmu_t(this, cfg->endianness, NULL); for (size_t i = 0; i < cfg->nprocs(); i++) { - procs[i] = new processor_t(&isa, cfg->varch(), this, cfg->hartids()[i], halted, - cfg->endianness, log_file.get(), sout_); + procs[i] = new processor_t(&isa, cfg, this, cfg->hartids()[i], halted, + log_file.get(), sout_); } make_dtb(); |