Add PLIC emulation

We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.

The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.

Signed-off-by: Anup Patel <anup@brainfault.org>

1 files changed, 8 insertions, 0 deletions

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 069e1b5..81a0cbc 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -98,6 +98,14 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
     bus.add_device(clint_base, clint.get());
   }
 
+  // create plic
+  reg_t plic_base;
+  uint32_t plic_ndev;
+  if (fdt_parse_plic(fdt, &plic_base, &plic_ndev, "riscv,plic0") == 0) {
+    plic.reset(new plic_t(procs, true, plic_ndev));
+    bus.add_device(plic_base, plic.get());
+  }
+
   //per core attribute
   int cpu_offset = 0, rc;
   size_t cpu_idx = 0;