diff options
| author | Tim Newsome <tim@sifive.com> | 2016-04-24 08:54:19 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | d999dfc0d41a119730ff8944d37dbee88bf99723 (patch) | |
| tree | 2268c9d7d5f122fb81253d10bd05901eaff0ff62 /riscv/riscv.mk.in | |
| parent | 191671a2015136c429394fd3051e4a9c1ff45352 (diff) | |
| download | spike-d999dfc0d41a119730ff8944d37dbee88bf99723.zip spike-d999dfc0d41a119730ff8944d37dbee88bf99723.tar.gz spike-d999dfc0d41a119730ff8944d37dbee88bf99723.tar.bz2 | |
Add debug_module bus device.
This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
Diffstat (limited to 'riscv/riscv.mk.in')
| -rw-r--r-- | riscv/riscv.mk.in | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index c7d84f7..279fbde 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -25,6 +25,7 @@ riscv_hdrs = \ insn_template.h \ mulhi.h \ gdbserver.h \ + debug_module.h \ riscv_precompiled_hdrs = \ insn_template.h \ @@ -47,6 +48,7 @@ riscv_srcs = \ rom.cc \ rtc.cc \ gdbserver.cc \ + debug_module.cc \ $(riscv_gen_srcs) \ riscv_test_srcs = |