From d999dfc0d41a119730ff8944d37dbee88bf99723 Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Sun, 24 Apr 2016 08:54:19 -0700
Subject: Add debug_module bus device.

This should replace the ROM hack I implemented earlier, but for now both
exist together.

Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
---
 riscv/riscv.mk.in | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'riscv/riscv.mk.in')

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index c7d84f7..279fbde 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -25,6 +25,7 @@ riscv_hdrs = \
 	insn_template.h \
 	mulhi.h \
 	gdbserver.h \
+	debug_module.h \
 
 riscv_precompiled_hdrs = \
 	insn_template.h \
@@ -47,6 +48,7 @@ riscv_srcs = \
 	rom.cc \
 	rtc.cc \
 	gdbserver.cc \
+	debug_module.cc \
 	$(riscv_gen_srcs) \
 
 riscv_test_srcs =
-- 
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