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| author | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-04-15 14:32:54 -0700 |
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| committer | Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU> | 2011-04-15 14:33:12 -0700 |
| commit | 481c9e8fd8a89106f70b73b6bd62e08f5b1e688a (patch) | |
| tree | 4551a5e0246bab24823f3caac4cd1a8b66782011 /riscv/riscv.ac | |
| parent | 402b4e8600281cb793bba0e493b37989a0db917f (diff) | |
| download | spike-481c9e8fd8a89106f70b73b6bd62e08f5b1e688a.zip spike-481c9e8fd8a89106f70b73b6bd62e08f5b1e688a.tar.gz spike-481c9e8fd8a89106f70b73b6bd62e08f5b1e688a.tar.bz2 | |
[sim] added icache simulator (disabled by default)
Diffstat (limited to 'riscv/riscv.ac')
| -rw-r--r-- | riscv/riscv.ac | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 36c701a..897b21f 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -18,6 +18,11 @@ AS_IF([test "x$enable_vec" != "xno"], [ AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) ]) +AC_ARG_ENABLE([icsim], AS_HELP_STRING([--disable-icsim], [Enable instruction cache simulator])) +AS_IF([test "x$enable_icsim" = "xyes"], [ + AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled]) +]) + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"]) |