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| author | Tim Newsome <tim@sifive.com> | 2016-05-04 18:51:26 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:12 -0700 |
| commit | dd233bc49946aa059b6ea9494b870d20076ce1b8 (patch) | |
| tree | c873d001c46e7935258091b1a938da53d54bbfd6 /riscv/processor.h | |
| parent | 6ef848928a5e2d72d9b0aed66f669b7b9a80b49a (diff) | |
| download | spike-dd233bc49946aa059b6ea9494b870d20076ce1b8.zip spike-dd233bc49946aa059b6ea9494b870d20076ce1b8.tar.gz spike-dd233bc49946aa059b6ea9494b870d20076ce1b8.tar.bz2 | |
Single step appears to work.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 9c2f7a6..721da2c 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -81,6 +81,14 @@ struct state_t uint32_t frm; bool serialized; // whether timer CSRs are in a well-defined state + // When true, execute a single instruction and then enter debug mode. This + // can only be set by executing dret. + enum { + STEP_NONE, + STEP_STEPPING, + STEP_STEPPED + } single_step; + reg_t load_reservation; #ifdef RISCV_ENABLE_COMMITLOG |