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authorDave.Wen <dave.wen@sifive.com>2020-05-20 07:11:31 -0700
committerDave.Wen <dave.wen@sifive.com>2020-05-20 08:01:59 -0700
commit5720fb6d79c67d4a18de367aa546a1728202a407 (patch)
tree432622bccb5634d7dd39bae2545d560ecb58dcf9 /riscv/processor.h
parent1c558aa3a1d40d689230002bc2d7b7f299b66978 (diff)
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add configurable LR/SC reservation set
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index 529a4f6..e5520e6 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -47,6 +47,7 @@ typedef struct
uint8_t cause;
} dcsr_t;
+
typedef enum
{
ACTION_DEBUG_EXCEPTION = MCONTROL_ACTION_DEBUG_EXCEPTION,
@@ -408,7 +409,6 @@ private:
FILE *log_file;
bool halt_on_reset;
std::vector<bool> extension_table;
-
std::vector<insn_desc_t> instructions;
std::map<reg_t,uint64_t> pc_histogram;