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author | Tim Newsome <tim@sifive.com> | 2017-08-07 11:21:58 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2017-08-07 11:21:58 -0700 |
commit | 4f8b6a69484bd901f213d9a73ea29d26c8022dfd (patch) | |
tree | 75407b6379802c0437771f1df1a7acff28505d02 /riscv/processor.h | |
parent | a327416eac285f50dcbb04e8ddf89204c66ece02 (diff) | |
download | spike-4f8b6a69484bd901f213d9a73ea29d26c8022dfd.zip spike-4f8b6a69484bd901f213d9a73ea29d26c8022dfd.tar.gz spike-4f8b6a69484bd901f213d9a73ea29d26c8022dfd.tar.bz2 |
Fix multicore debug.
In an older implementation I was thinking of having different entry
points for different harts, but that's no longer true.
Also get rid of a bunch of trailing whitespace.
Diffstat (limited to 'riscv/processor.h')
-rw-r--r-- | riscv/processor.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 071f458..6e8d684 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -194,12 +194,6 @@ public: bool slow_path(); bool halted() { return state.dcsr.cause ? true : false; } bool halt_request; - // The unique debug rom address that this hart jumps to when entering debug - // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive. - uint32_t debug_rom_entry() { - fprintf(stderr, "Debug_rom_entry called for id %d = %x\n", id, DEBUG_ROM_ENTRY + 4*id); - return DEBUG_ROM_ENTRY + 4 * id; - } // Return the index of a trigger that matched, or -1. inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data) |