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| author | Christopher Celio <celio@eecs.berkeley.edu> | 2014-08-15 15:38:41 -0700 |
|---|---|---|
| committer | Christopher Celio <celio@eecs.berkeley.edu> | 2014-08-15 15:38:41 -0700 |
| commit | 616cc32c30ac0684edfd50ed44fc78ed1bc20884 (patch) | |
| tree | 3ad9cbea79da5a40a5a351e842e1e890a07ad298 /riscv/processor.h | |
| parent | e2c0c3021ac2fa7cad5866e0f100c2dbf2372986 (diff) | |
| download | spike-616cc32c30ac0684edfd50ed44fc78ed1bc20884.zip spike-616cc32c30ac0684edfd50ed44fc78ed1bc20884.tar.gz spike-616cc32c30ac0684edfd50ed44fc78ed1bc20884.tar.bz2 | |
Added PC histogram option.
- Spits out all PCs (on 4B granularity) executed with count.
- Requires a compile time configuration option.
- Also requires a run-time flag.
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 41268f9..58c31cb 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -6,6 +6,7 @@ #include "config.h" #include <cstring> #include <vector> +#include <map> class processor_t; class mmu_t; @@ -69,6 +70,7 @@ public: ~processor_t(); void set_debug(bool value); + void set_histogram(bool value); void reset(bool value); void step(size_t n); // run for n cycles void deliver_ipi(); // register an interprocessor interrupt @@ -81,6 +83,7 @@ public: state_t* get_state() { return &state; } extension_t* get_extension() { return ext; } void yield_load_reservation() { state.load_reservation = (reg_t)-1; } + void update_histogram(size_t pc); void register_insn(insn_desc_t); void register_extension(extension_t*); @@ -94,11 +97,13 @@ private: uint32_t id; bool run; // !reset bool debug; + bool histogram_enabled; bool rv64; std::vector<insn_desc_t> instructions; std::vector<insn_desc_t*> opcode_map; std::vector<insn_desc_t> opcode_store; + std::map<size_t,size_t> pc_histogram; void take_interrupt(); // take a trap if any interrupts are pending void take_trap(trap_t& t); // take an exception |