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authorChih-Min Chao <chihmin.chao@sifive.com>2019-06-06 02:54:46 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2019-06-14 07:42:30 -0700
commit48fe0c484d50073bd5d12bdb7fef5b7ea257e006 (patch)
tree3ebf533ff93788a3d2cf71308df568df117c53b1 /riscv/processor.h
parent9de0cdda3f089bf1a73d39eb1abb1dafe8cdbbab (diff)
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rvv: add varch option parser and initialize vector unit
the default vector parameters are defined in configuration time but can be changed throught command-line option Signed-off-by: Dave Wen <dave.wen@sifive.com>
Diffstat (limited to 'riscv/processor.h')
-rw-r--r--riscv/processor.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/processor.h b/riscv/processor.h
index cd4355d..8e68fb3 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -282,7 +282,8 @@ static int cto(reg_t val)
class processor_t : public abstract_device_t
{
public:
- processor_t(const char* isa, simif_t* sim, uint32_t id, bool halt_on_reset=false);
+ processor_t(const char* isa, const char* varch, simif_t* sim, uint32_t id,
+ bool halt_on_reset=false);
~processor_t();
void set_debug(bool value);
@@ -446,6 +447,7 @@ private:
friend class clint_t;
friend class extension_t;
+ void parse_varch_string(const char* isa);
void parse_isa_string(const char* isa);
void build_opcode_map();
void register_base_instructions();