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| author | Andrew Waterman <andrew@sifive.com> | 2019-11-13 05:22:18 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-13 05:22:18 -0800 |
| commit | 2704790df5d16868571bacf4c521df4bac87f452 (patch) | |
| tree | 5b80d59e0eb989d491f2c7db46a1a960e8236e67 /riscv/processor.h | |
| parent | ff81dea8593c6e51b45e7bed230a2cafd56e4caf (diff) | |
| parent | 86857aa3511d0a3bb1d28f8a6213013382545f77 (diff) | |
| download | spike-2704790df5d16868571bacf4c521df4bac87f452.zip spike-2704790df5d16868571bacf4c521df4bac87f452.tar.gz spike-2704790df5d16868571bacf4c521df4bac87f452.tar.bz2 | |
Merge pull request #356 from riscv/priv-flag
Add --priv command-line option to set which privilege modes are available
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 3e72282..bcf36c5 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -297,8 +297,8 @@ static int cto(reg_t val) class processor_t : public abstract_device_t { public: - processor_t(const char* isa, const char* varch, simif_t* sim, uint32_t id, - bool halt_on_reset=false); + processor_t(const char* isa, const char* priv, const char* varch, + simif_t* sim, uint32_t id, bool halt_on_reset=false); ~processor_t(); void set_debug(bool value); @@ -465,8 +465,9 @@ private: friend class clint_t; friend class extension_t; - void parse_varch_string(const char* isa); - void parse_isa_string(const char* isa); + void parse_varch_string(const char*); + void parse_priv_string(const char*); + void parse_isa_string(const char*); void build_opcode_map(); void register_base_instructions(); insn_func_t decode_insn(insn_t insn); |