Generate device tree for target machine

1 files changed, 8 insertions, 2 deletions

diff --git a/riscv/processor.h b/riscv/processor.h
index fe0a121..b9564d6 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -4,6 +4,7 @@
 
 #include "decode.h"
 #include "config.h"
+#include "devices.h"
 #include <cstring>
 #include <vector>
 #include <map>
@@ -72,7 +73,7 @@ struct state_t
 };
 
 // this class represents one processor in a RISC-V machine.
-class processor_t
+class processor_t : public abstract_device_t
 {
 public:
   processor_t(const char* isa, sim_t* sim, uint32_t id);
@@ -82,7 +83,6 @@ public:
   void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
-  void deliver_ipi(); // register an interprocessor interrupt
   bool running() { return run; }
   void set_csr(int which, reg_t val);
   void raise_interrupt(reg_t which);
@@ -91,6 +91,7 @@ public:
   state_t* get_state() { return &state; }
   extension_t* get_extension() { return ext; }
   bool supports_extension(unsigned char ext) {
+    if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
     return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
   }
   void push_privilege_stack();
@@ -101,6 +102,10 @@ public:
   void register_insn(insn_desc_t);
   void register_extension(extension_t*);
 
+  // MMIO slave interface
+  bool load(reg_t addr, size_t len, uint8_t* bytes);
+  bool store(reg_t addr, size_t len, const uint8_t* bytes);
+
 private:
   sim_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu
@@ -111,6 +116,7 @@ private:
   uint32_t id;
   int max_xlen;
   int xlen;
+  std::string isa;
   bool run; // !reset
   bool debug;
   bool histogram_enabled;