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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-07-04 21:31:09 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-08-09 15:45:15 +0800 |
| commit | ba10686fd18f3fbb036ca04b906deb57e7d1fe54 (patch) | |
| tree | a3d7fb6ac1c8b2d531203cfb8402b02e1d9ed767 /riscv/processor.h | |
| parent | 5672c4a41ad7a9af011d385962c175a5a6012fd9 (diff) | |
| download | spike-ba10686fd18f3fbb036ca04b906deb57e7d1fe54.zip spike-ba10686fd18f3fbb036ca04b906deb57e7d1fe54.tar.gz spike-ba10686fd18f3fbb036ca04b906deb57e7d1fe54.tar.bz2 | |
add support for sscofpmf extension v0.5.2
since spike doesn't truly support counting of hardware performance events,
only csr related read/write functions is supported currently
Diffstat (limited to 'riscv/processor.h')
| -rw-r--r-- | riscv/processor.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.h b/riscv/processor.h index 88ddf70..9b821b3 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -145,6 +145,7 @@ struct state_t csr_t_p medeleg; csr_t_p mideleg; csr_t_p mcounteren; + csr_t_p mevent[29]; csr_t_p scounteren; csr_t_p sepc; csr_t_p stval; |