From ba10686fd18f3fbb036ca04b906deb57e7d1fe54 Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Mon, 4 Jul 2022 21:31:09 +0800 Subject: add support for sscofpmf extension v0.5.2 since spike doesn't truly support counting of hardware performance events, only csr related read/write functions is supported currently --- riscv/processor.h | 1 + 1 file changed, 1 insertion(+) (limited to 'riscv/processor.h') diff --git a/riscv/processor.h b/riscv/processor.h index 88ddf70..9b821b3 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -145,6 +145,7 @@ struct state_t csr_t_p medeleg; csr_t_p mideleg; csr_t_p mcounteren; + csr_t_p mevent[29]; csr_t_p scounteren; csr_t_p sepc; csr_t_p stval; -- cgit v1.1