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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-22 00:19:36 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-22 00:19:53 -0700 |
commit | 5e5fa12bdf617b0a4537fd6b0da49816cd05f1c1 (patch) | |
tree | b2384dd23048d7b8fcf00af6999386350d17ed15 /riscv/processor.cc | |
parent | 316ae3888dae19bbb27d4dbd719d1bc0fb39a9e0 (diff) | |
download | spike-5e5fa12bdf617b0a4537fd6b0da49816cd05f1c1.zip spike-5e5fa12bdf617b0a4537fd6b0da49816cd05f1c1.tar.gz spike-5e5fa12bdf617b0a4537fd6b0da49816cd05f1c1.tar.bz2 |
rvv: totally remove vlmul field
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r-- | riscv/processor.cc | 31 |
1 files changed, 6 insertions, 25 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 34ab01c..9db3f6a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -377,39 +377,20 @@ void processor_t::vectorUnit_t::reset(){ } reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newType){ - reg_t vlmul = 0; + int vlmul = 0; if (vtype != newType){ vtype = newType; vsew = 1 << (BITS(newType, 4, 2) + 3); - vlmul = BITS(newType, 1, 0); - vemul = vlmul; + vlmul = (BITS(newType, 5, 5) << 2) | BITS(newType, 1, 0); + vlmul = (int8_t)(vlmul << 5) >> 5; + vflmul = vlmul >= 0 ? 1 << vlmul : 1.0 / (1 << -vlmul); + vlmax = (VLEN/vsew) * vflmul; + vemul = vflmul; veew = vsew; - fractional_lmul = BITS(newType, 5, 5); vta = BITS(newType, 6, 6); vma = BITS(newType, 7, 7); vediv = 1 << BITS(newType, 9, 8); - if (fractional_lmul) { - switch(vlmul){ - case 3: - vlmul = 2; - break; - case 2: - vlmul = 4; - break; - case 1: - vlmul = 8; - break; - } - vlmax = (VLEN/vsew)/vlmul; - vflmul = 1.0/vlmul; - vlmul = 1; - } else { - vlmul = 1 << vlmul; - vlmax = VLEN/vsew * vlmul; - vflmul = vlmul; - } - vill = !(vflmul >= 0.125 && vflmul <= 8) || vsew > ELEN || vediv != 1 || (newType >> 8) != 0; if (vill) { vlmax = 0; |