diff options
| author | Tim Newsome <tim@sifive.com> | 2022-03-16 10:55:39 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:10:03 -0700 |
| commit | f9c90d729bd9d5772a2a3a320da094d6426911cf (patch) | |
| tree | 3f9612347e5e5823ecf5ff81767d83516f86a554 /riscv/processor.cc | |
| parent | 354f977848c17ba80681de60c05d46966e1ffc1a (diff) | |
| download | spike-f9c90d729bd9d5772a2a3a320da094d6426911cf.zip spike-f9c90d729bd9d5772a2a3a320da094d6426911cf.tar.gz spike-f9c90d729bd9d5772a2a3a320da094d6426911cf.tar.bz2 | |
Give triggers::module_t its own processor_t*
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 5d0e5bc..5aae1f2 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -32,6 +32,7 @@ processor_t::processor_t(isa_parser_t isa, const char* varch, impl_table(256, false), last_pc(1), executions(1), TM(state.num_triggers) { VU.p = this; + TM.proc = this; #ifndef __SIZEOF_INT128__ if (extension_enabled('V')) { |