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authorTim Newsome <tim@sifive.com>2022-03-30 10:18:02 -0700
committerTim Newsome <tim@sifive.com>2022-04-05 10:33:31 -0700
commitf381b841ceaf816745604b40b34c951f01d8d6d4 (patch)
treeb05a011f0e1a92c5341b0381a4228212ef712be0 /riscv/processor.cc
parent306b519e7a6e9eb8b3c5cf3942c0e8cd92d145ca (diff)
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Abstract away access to load/store/execute bits.
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r--riscv/processor.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index f626a78..83f1473 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -996,13 +996,13 @@ void processor_t::trigger_updated(const std::vector<triggers::mcontrol_t *> *tri
mmu->check_triggers_store = false;
for (auto trigger : *triggers) {
- if (trigger->execute) {
+ if (trigger->execute()) {
mmu->check_triggers_fetch = true;
}
- if (trigger->load) {
+ if (trigger->load()) {
mmu->check_triggers_load = true;
}
- if (trigger->store) {
+ if (trigger->store()) {
mmu->check_triggers_store = true;
}
}