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authorAndrew Waterman <andrew@sifive.com>2022-04-07 09:51:39 -0700
committerAndrew Waterman <andrew@sifive.com>2022-04-07 09:51:39 -0700
commitdba7efaf9e2e8d5251820c8555a184f715bb4d46 (patch)
tree9076c2b2607f2cfce0c434259692be08f1a72f2f /riscv/processor.cc
parente52327deeefb29908a822a9eb2f6fc5c87e968af (diff)
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Rename processor_t::set_csr to put_csr to fix build on RISC-V
The alternative would be to #undef set_csr after including encoding.h, but this solution strikes me as cleaner. Part of the reason is that set_csr was not a great name: it sounds like it implements the CSRRS (read & set) instruction, rather than impelementing a simple write.
Diffstat (limited to 'riscv/processor.cc')
-rw-r--r--riscv/processor.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc
index e6783bf..3b8d2ec 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -496,8 +496,8 @@ void processor_t::reset()
if (n_pmp > 0) {
// For backwards compatibility with software that is unaware of PMP,
// initialize PMP to permit unprivileged access to all of memory.
- set_csr(CSR_PMPADDR0, ~reg_t(0));
- set_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
+ put_csr(CSR_PMPADDR0, ~reg_t(0));
+ put_csr(CSR_PMPCFG0, PMP_R | PMP_W | PMP_X | PMP_NAPOT);
}
for (auto e : custom_extensions) // reset any extensions
@@ -838,7 +838,7 @@ int processor_t::paddr_bits()
return max_xlen == 64 ? 50 : 34;
}
-void processor_t::set_csr(int which, reg_t val)
+void processor_t::put_csr(int which, reg_t val)
{
val = zext_xlen(val);
auto search = state.csrmap.find(which);