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| author | Andrew Waterman <andrew@sifive.com> | 2022-09-22 17:34:33 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-04 15:40:01 -0700 |
| commit | ce69fb5db97ecf240336b7826dd9dddeb32e5dca (patch) | |
| tree | f78647d0eafa9abc414f5ded2a3663c7506cfd9c /riscv/processor.cc | |
| parent | a51e44ed228e48fc1dbf24ec7dc23cbd61a7874a (diff) | |
| download | spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.zip spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.gz spike-ce69fb5db97ecf240336b7826dd9dddeb32e5dca.tar.bz2 | |
Suppress most unused variable warnings
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 5ae6bbb..9bb7d04 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -960,7 +960,7 @@ reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) throw trap_illegal_instruction(insn.bits()); } -reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc) +reg_t illegal_instruction(processor_t UNUSED *p, insn_t insn, reg_t UNUSED pc) { // The illegal instruction can be longer than ILEN bits, where the tval will // contain the first ILEN bits of the faulting instruction. We hard-code the |