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| author | Tim Newsome <tim@sifive.com> | 2022-05-19 17:11:07 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-19 17:11:07 -0700 |
| commit | a0298a33e7b2091ba8d9f3a20838d96dc1164cac (patch) | |
| tree | f6227ea4d52123b92c7236616317fbba149e2733 /riscv/processor.cc | |
| parent | 32eeb5a2b2ba6960f3379b23fa41b67ad0a4e38b (diff) | |
| download | spike-a0298a33e7b2091ba8d9f3a20838d96dc1164cac.zip spike-a0298a33e7b2091ba8d9f3a20838d96dc1164cac.tar.gz spike-a0298a33e7b2091ba8d9f3a20838d96dc1164cac.tar.bz2 | |
Move ebreak* logic from take_trap into instructions. (#1006)
Now that logic only affects ebreak instructions, and does not affect
triggers that also cause a trap to be taken.
Fixes #725. Although like Paul, I don't have a test for this case.
Introduce trap_debug_mode so so ebreak instructions can force entry into
debug mode.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index a9003a8..bb41248 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -720,14 +720,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) return; } - if (t.cause() == CAUSE_BREAKPOINT && ( - (state.prv == PRV_M && state.dcsr->ebreakm) || - (state.prv == PRV_S && state.dcsr->ebreaks) || - (state.prv == PRV_U && state.dcsr->ebreaku))) { - enter_debug_mode(DCSR_CAUSE_SWBP); - return; - } - // By default, trap to M-mode, unless delegated to HS-mode or VS-mode reg_t vsdeleg, hsdeleg; reg_t bit = t.cause(); |