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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2021-11-27 14:01:14 +0900 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-11-27 14:58:33 -0800 |
| commit | 9b97d3112d12395bd9a4b014ec7eaca5e5328da1 (patch) | |
| tree | 6b90757e331f04034d962dc150f7079828e14cae /riscv/processor.cc | |
| parent | 5af02ff88228b946f4aeccf22871c84463220a6e (diff) | |
| download | spike-9b97d3112d12395bd9a4b014ec7eaca5e5328da1.zip spike-9b97d3112d12395bd9a4b014ec7eaca5e5328da1.tar.gz spike-9b97d3112d12395bd9a4b014ec7eaca5e5328da1.tar.bz2 | |
Accept dummy extension: "ZiHintPause"
"ZiHintPause" extension adds PAUSE instruction (which is a special
encoding of FENCE instruction) that performs nothing in the simulator
but supported by its disassembler.
This commit adds dummy extension (which does nothing itself)
"ZiHintPause" to `processor_t::parse_isa_string` to prevent
"unsupported extension" error message.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 5f62d8e..55c48d5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -257,6 +257,8 @@ void processor_t::parse_isa_string(const char* str) } else if (ext_str == "zifencei") { // For compatibility with version 2.0 of the base ISAs, we // unconditionally include FENCE.I, so Zifencei adds nothing more. + } else if (ext_str == "zihintpause") { + // HINTs encoded in base-ISA instructions are always present. } else if (ext_str == "zmmul") { extension_table[EXT_ZMMUL] = true; } else if (ext_str == "zba") { |