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| author | Tim Newsome <tim@sifive.com> | 2022-03-24 11:30:07 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-05 10:33:31 -0700 |
| commit | 825b396c4dba96f9941fdc4a38301e890c8c9d12 (patch) | |
| tree | da50ffe592de3d39513b3f09de4492a0c701e67d /riscv/processor.cc | |
| parent | 972943662c6e608e5d321c9128cdb9aaf903a4ae (diff) | |
| download | spike-825b396c4dba96f9941fdc4a38301e890c8c9d12.zip spike-825b396c4dba96f9941fdc4a38301e890c8c9d12.tar.gz spike-825b396c4dba96f9941fdc4a38301e890c8c9d12.tar.bz2 | |
Move num_triggers knowledge into triggers.h
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 5aae1f2..0543c26 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -29,7 +29,7 @@ processor_t::processor_t(isa_parser_t isa, const char* varch, : debug(false), halt_request(HR_NONE), isa(isa), sim(sim), id(id), xlen(0), histogram_enabled(false), log_commits_enabled(false), log_file(log_file), sout_(sout_.rdbuf()), halt_on_reset(halt_on_reset), - impl_table(256, false), last_pc(1), executions(1), TM(state.num_triggers) + impl_table(256, false), last_pc(1), executions(1), TM(4) { VU.p = this; TM.proc = this; @@ -173,8 +173,6 @@ static int xlen_to_uxl(int xlen) abort(); } -const int state_t::num_triggers; - void state_t::reset(processor_t* const proc, reg_t max_isa) { pc = DEFAULT_RSTVEC; @@ -997,14 +995,14 @@ void processor_t::trigger_updated() mmu->check_triggers_load = false; mmu->check_triggers_store = false; - for (unsigned i = 0; i < state.num_triggers; i++) { - if (TM.triggers[i]->execute) { + for (auto trigger : TM.triggers) { + if (trigger->execute) { mmu->check_triggers_fetch = true; } - if (TM.triggers[i]->load) { + if (trigger->load) { mmu->check_triggers_load = true; } - if (TM.triggers[i]->store) { + if (trigger->store) { mmu->check_triggers_store = true; } } |