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| author | Andrew Waterman <andrew@sifive.com> | 2022-06-06 20:36:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-06-06 20:54:17 -0700 |
| commit | 7d943d740afb6a42b50c979800608c6fb1614d0c (patch) | |
| tree | e92f3f4934f50ad1f8957441dd026a275d8d75b9 /riscv/processor.cc | |
| parent | d2020b3256cf9a832cbbfe7a32c5753abe75cb7d (diff) | |
| download | spike-7d943d740afb6a42b50c979800608c6fb1614d0c.zip spike-7d943d740afb6a42b50c979800608c6fb1614d0c.tar.gz spike-7d943d740afb6a42b50c979800608c6fb1614d0c.tar.bz2 | |
Don't mask instruction bits
No longer needed, since they are no longer sign-extended.
Fixes #1022 by eliminating undefined behavior (64-bit instructions
resulted in a shift amount equal to the datatype width).
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index bb41248..c4ca0bc 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -796,7 +796,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) void processor_t::disasm(insn_t insn) { - uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1); + uint64_t bits = insn.bits(); if (last_pc != state.pc || last_bits != bits) { std::stringstream s; // first put everything in a string, later send it to output |